VARIATION-AWARE CUSTOM IC DESIGN BEST PRACTICES - DAC 2014

Monday, June 2, 2014, 10:30 AM - 11:30 AM
Room 236/238, Moscone Center, San Francisco

Speakers:
- Broadcom - Mark Erikson
- Seoul National University - Jaeha Kim
- Sidense - Irina Ilatov
- Solido Design Automation - Trent McConaghy

Panel discussion will focus on best practices and methodologies for variation-aware memory, standard cell, analog/RF, and custom digital design. Panel topics will span 4- to 6-sigma Monte Carlo verification, high-sigma cell optimization, 3-sigma Monte Carlo verification, verification across 100,000+ PVT/parasitic corners and statistical PVT corners, FinFET variation, variation debug, analog calibration/trimming and simulation requirements for variation analysis.

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VARIATION-AWARE CUSTOM IC DESIGN BEST PRACTICES PANEL

Seating is limited - please pre-register below. You will receive a registration confirmation note.

You only need an 'exhibits badge' to attend the panel, and if you register for DAC by May 15, the exhibits badge is free.You can go to the URL below, select exhibits only and then "I Love DAC" for free registration.

https://reg.mpassociates.com/reglive/PromoCode.aspx?confid=170

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