ITC 2016 Poster Session Survey

Poster 1.1: Double Pumped Memory Fault Modeling and Test
S. Adham, J-D. Yu, A. Lai, H. Liao, C. O'Connell, TSMC

Poster 1.2: Tester Performance Validation (TPV): Methods and Apparatus for Validating Adherence to Published Specs in the Tester Acceptance Process
N. Magdaleno, M. Mohammed, Texas Instruments

Poster 1.3: Does Your Locking SIB Have a Back Door?
S. Kancharla, S. Gupta, J. Kayse, J. Dworak, D. Engels, Southern Methodist University; A. Crouch, SiliconAid Solutions

Poster 1.4: Custom Logic BIST in Cutting-Edge SoC FPGA Systems
R. Rajanarayanan, N. Varma, Achronix Semiconductor; A. Cron, Synopsys

Poster 1.5: Testing for Connectivity to DDR Memory at Board- and System-Level ; Challenges, Guidance and Success for Boundary-Scan-based Methods
A. Ley, ASSET InterTech

Poster 1.6: Use EDT Dynamic Bandwidth Management to Reduce SoC Patterns
K. Huang, B. Lu, T. Li, L. Xu, Spreadtrum Communications; Y. Huang, F. Meng, Mentor Graphics

Poster 1.7: Fault-tolerant Photonic Router for Network-on-Chip with High Reliability
D. Dang, P. Biswas, D. Walker, R. Mahapatra, Texas A&M University

Poster 1.8: Diagnosing Cell Internal Defects for FinFET Technology
H. Tang, W. Yang, M. Abdelwahid, D. Han, Samsung; S. Park, Mentor Graphics

Poster 1.9: Exploit Faster-Than-At-Speed Functional Programs Execution for Burn-In Test
A. Bosio, G. Di Natale, LIRMM - Universit de Montpellier II / CNRS; P. Bernardi, A. Guerriero, F. Venini, politecnico di torino

Poster 1.10: Note on Critical-Area-aware Test Pattern Generation and Reordering
S. Inuyama, K. Iwasaki, Tokyo Metropolitan University; M. Arai, Nihon University

Poster 1.11: Silicon Debug on ATE Using Protocol-aware JTAG-IJTAG EDA Software Tools
A. Crouch, J. Johnson, SiliconAid Solutions; N. Poulson, Advantest

Poster 1.12: Assessing Diagnostic Coverage by Transient Fault Injection for ISO 26262
J. Schat, NXP Semiconductors

Poster 1.13: Uninterrupted Hardware Design
X. Qin, H. Li, Z. Wang, Huawei

Poster 1.14: Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra
D. Walker, P. Biswas, Texas A&M University

Poster 1.15: ASICS End-to-End Automated Test Program Generation and Diagnostics Enablement
D. Sprague, R. Bulaga, GLOBALFOUNDRIES

Poster 1.16: Yield Improvement by Optimizing the Impedance of Power Delivery Network (PDN) on Device Interface Board (DIB)
J. Shi, Spreadtrum Communications; Z. Chen, Y. Huang, Mentor Graphics; P. Zhang, Teradyne

Poster 1.17: 1687.1 -- New Connections for a New Standard
A. Crouch, J. Johnson, SiliconAid Solutions; M. Keim, Mentor Graphics

Poster 1.18: Combining Channel Sharing and Hierarchical DFT Techniques to Address Pin-limited, Large SoC Challenges
Z. Zhang, L. Kong, K. Huang, B. Lu, Spreadtrum Communications; R. Fisette, F. Meng, Mentor Graphics

Poster 1.19: A Smart Software Approach to Implement Real-Time Dynamic Part Average Testing in Production
C. Tsao, Y-T. Hsu, Sigurd Microelectronics

Poster 1.20: CloudTesting Service In Silicon Diagnostics
A. Sivaram, O. Yasuji, Advantest; B. Zhang, D. Mark, J. Fan, Xilinx

Poster 1.21: An IJTAG-compatible IDDT Embedded Instrument for Health Monitoring and Prognostics
H. Kerkhoff, A. Ibrahim, University of Twente

Poster 1.22. ECU Testing with Adaptive Random Walks
B. Fath, KIT; F. Gauterin, Karlsruhe Institute of Technology

Poster 1.23. Test Matrix Architecture to Test and On-the-Fly Failure Isolation on multiple Instance of Heterogeneous Cores
B. Konda, J. Udyavar, S. Ahmed, S. Kumar, GLOBALFOUNDRIES; M. Lakshmanan, Cadence Design Systems

Poster 1.24, Scalable and Reusable Dependability Framework Based on IEEE 1687
A. Ibrahim, H. Kerkhoff, University of Twente

ITC 2016 Poster Session

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