Thank you for taking the time to answer a quick 10-minute survey regarding end-user expectations of a PDK for i3M's Heterogeneous System in a Package (HSIP) technology.  HSIP is a Fan-Out Wafer Level Packaging capability that embeds active and passive IC's in a thin core with copper interconnect layers on one or both sides surrounding that core.  Common configurations include one or many IC components in the core with as many as 7 copper layers per side.  Through-core connections are handled in solid copper through-via.

This survey is to better understand your use of electrical design tools from previous works, such that the HSIP PDK from i3 Microsystems can be well aligned to your needs.

For more information about HSIP, go to www.i3microsystems.com

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* 1. When thinking of previous electrical designs, how much automation do you typically use in your electrical design work flow?

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* 2. When thinking of previous electrical designs, do you write your own scripts in-house? (Check all that apply)

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* 3. Which design tools do you use for Schematic Capture? (Check all that Apply)

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* 4. Which design tools do you use for Physical Design & (Mask) Layout?

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* 5. Which tools if any do you use for Automatic Place and Route?

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* 6. Which design tools do you use for DRC check and LVS?

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* 7. Which languages do you use for digital simulation?

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* 8. Which tools do you use for digital simulation?

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* 9. Which tools do you use for analog/RF simulation?

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* 10. When thinking of likely HSIP designs, which types of simulation and/or design verifications do you plan to perform?

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* 11. When thinking of other advanced electronic components or assemblies, do you have a formal, written procedure when completing a design before sending to the factory partner for fabrication?

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* 12. How many HSIP designs have you and/or your team completed and have had manufactured?

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* 13. How many HSIP parts do you expect you will need manufactured all-time of your next HSIP design?

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* 14. What level of complexity do you expect in your next HSIP design? (CHECK ALL THAT APPLY)

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* 15. What is the minimum embedded IC or passive die pad pitch in your next HSIP design?

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* 16. What is the minimum final HSIP package pin or ball pitch on your next design? (This is the ball pitch of the final HSIP component to mate with the outer world)

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* 17. If present in your design, what is the minimum SMT device pitch on your next HSIP design?

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* 18. When you plan to design your HSIP for Production, do you plan to execute mechanical and thermal simulations beforehand?

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* 19. Do you have any other special considerations in your next HSIP design? (CHECK ALL THAT APPLY)

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* 20. My electrical component design team has the following team size and experience level (answer by checking one box int he grid based on your division level resources of the company)

  total of 5-10 years combined design experience total of 10 - 25 years combined design experience total of over 25 years combined design experience
1 heroic team member
2 - 3 members
3 - 10 members
more than 10 members

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* 21. If willing to identify yourself, please indicate the primary contact for design / your name and email address

0 of 21 answered
 

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