ITC 2016 Session 2 - DFT
Peter Wohl, Synopsys (Chair)
Vivek Chickermane, Cadence (Discussant)
2.1: Test Point Insertion in Hybrid Test Compression/LBIST Architectures
J. Rajski, Mentor Graphics
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2.2: A Unified Test and Fault-tolerant Multicast Solution for Network-on-Chip Designs
D. Xiang, Tsinghua University
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2.3: Putting Wasted Clock Cycles to Use: Enhancing Fortuitous Cell-aware Fault Detection with Scan Shift Capture
F. Zhang, Southern Methodist University
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2.4: Minimal-Area Test Points for Deterministic Patterns
Y. Liu, University of Iowa
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