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* 4.1: Defect Tolerance for CNFET-based SRAMs
T. Li, Spreadtrum Communications

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* 4.2: A Built-in Self-Repair Scheme for DRAMs with Spare Rows, Columns, and Bits
Y-X Chen, National Central University

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* 4.3: EMACS: Efficient MBIST Architecture for Test and Characterization of STT-MRAM Arrays
I. Yoon, Georgia Institute of Technology

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