DVCon Europe 2020 Best Paper and Poster Voting Survey

Submit your vote before Thursday October 28, 17:15 CET.

P1.1 Does it pay off to add Portable Stimulus Layer on top of UVM IP block test bench?

P1.2 Make your Testbenches Run Like Clockwork!

P1.3 A Comprehensive Verification Platform for RISC-V based Processors

P1.4 Mutable Verification Environments through Visitor and Dynamic Register map Configuration

P1.5 Facilitating Transactions in VHDL and SystemVerilog

P1.6 Lean Verification Techniques: Executable SystemVerilog UVM Defect Table For Simulations

P2.1 A Methodology to Verify Functionality, Security, and Trust for RISC-V Cores

P2.2 Build Reliable and Efficient Reset Networks with a Comprehensive Reset Domain Crossing Verification Solution

P2.3 Model-based Automation of Verification Development for automotive SOCs

P2.4 Discovering Deadlocks in a Memory Controller IP

P2.5 How To Verify Encoder And Decoder Designs Using Formal Verification

P2.6 Using Formal to Prevent Deadlocks

P3.1 Boosting Mixed-signal Design Productivity with FPGA-based Methods Throughout the Chip Design Process

P3.2 SOBEL FILTER: Software Implementation to RTL using High Level Synthesis

P3.3 Single Source System to Register-Transfer Level Design Methodology Using High-Level Synthesis

P3.4 Mixed Electronic System Level Power/Performance Estimation using SystemC/TLM2.0 Modeling and PwClkARCH library

P3.5 Timing-Aware High Level Power Estimation of Industrial Interconnect Module

P3.6 Clock Controller Unit Design Metrics: Area, Power, Software flexibility and Congestion Impacts at System Level

P4.1 Enhancing Quality and Coverage of CDC Closure in Intel’s SoC Design

P4.2 Static Analysis of SystemC/SystemC-AMS System and Architectural Level Models

P4.3 Bit Density-based Pre-characterization of RAM Cells for Area Critical SOC Design

P4.4 Temporal Assertions in SystemC

P4.5 Accelerating and Improving FPGA Design Reviews Using Analysis Tools

P4.6 Accelerating Automotive Ethernet validation by leveraging Synopsys Virtualizer with TraceCompass

P5.1 An Automated Pre-silicon IP Trustworthiness Assessment for Hardware Assurance

P5.2 Deploying HLS in a DO-254/ED-80 Workflow

P5.3 Experience of using Formal Verification for a Complex Memory Subsystem Design

P5.4 Analog Modelling to Suit Emulation for Hardware-Software Co-Verification

P5.5 A step towards Zero Silicon Bugs using Assertion based Assumption Validation

P5.6 IP-Coding Style Variants in a Multi-layer Generator Framework

P5.7 Probing UPF Dynamic Objects: Methodologies to Build Your Custom Low-Power Verification Platform

P5.8 Automatic Diagram Creation for Design and Testbenches

P5.9 Formal Verification Experiences: Silicon Bug Hunt with “Deep Sea Fishing”

P5.10 Achieving Faster Reset Verification Closure with Intelligent Reset Domain Crossings Detection

P5.11 Verification of a Multi-languages Components - A Case Study: Specman E Environment with SystemVerilog UVM UVC