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Survey Questions

Please complete our brief "Verification Complexity" survey for a chance to win a free Apple iPad.

Your answers will remain confidential.

1. What is your job title?

What is your job title? Verification engineer

Verification engineering manager

Design engineer

Design engineering manager

Director

Other (please specify)

2. What category best describes your current or most recent design project?

What category best describes your current or most recent design project? Processor

Graphics

Networking

Communications

Mobile

Storage

Memory

Automotive

Mil/Aero

Medical

Other (please specify)

3. What is the size (in instances) of your current or most recent design?

What is the size (in instances) of your current or most recent design? Less than 1 million

1 million to 10 million

10 million to 50 million

50 million to 100 million

More than 100 million

4. For what is your current or most recent design targeted?

For what is your current or most recent design targeted? ASIC / ASSP / Standard cells

FPGA

Both (ASIC / ASSP / Standard cells and FPGA)

None of the above

5. If you selected "ASIC / ASSP / Standard cells" or "Both" in question #4 above, what is the process geometry of your current or most recent design?

If you selected "ASIC / ASSP / Standard cells" or "Both" in question #4 above, what is the process geometry of your current or most recent design? Didn't select "ASIC / ASSP / Standard cells"

32nm or below

40-45nm

65nm

90nm

130nm

180nm

Other (please specify)

6. How many interface and bus protocols are supported in your current or most recent design?

How many interface and bus protocols are supported in your current or most recent design? None

1 or 2

2 to 5

More than 5

7. For your current or most recent design, what percentage of reused lines of RTL are/were used at chip level (compared to total lines of RTL)?

For your current or most recent design, what percentage of reused lines of RTL are/were used at chip level (compared to total lines of RTL)? Less than 25%

Between 25% and 50%

Between 50% and 75%

More than 75%

8. For your current or most recent design environment, what is/was the ratio of lines of code in testbench to lines of code in RTL?

For your current or most recent design environment, what is/was the ratio of lines of code in testbench to lines of code in RTL? Less than 1:1

Between 1:1 and 5:1

Between 5:1 and 10:1

More than 10:1

9. Which verification capabilities/technologies are/were used in your current or most recent project? (Check all that apply.)

Which verification capabilities/technologies are/were used in your current or most recent project? (Check all that apply.) SystemVerilog testbench Coverage Constraint solver Assertions Structured methodology Verilog	SystemC VHDL Integrated Development Environment (IDE) Debug Regression management Planning	Multi-voltage (low power) simulation Verification IP (VIP) FPGA-based prototyping Virtual prototyping Emulation
Other (please specify)

10. Please rank the importance of each of the following capabilities/technologies. (1 is least important; 5 is most important.)

	1	2	3	4	5
SystemVerilog testbench	*Please rank the importance of each of the following capabilities/technologies. (1 is least important; 5 is most important.) SystemVerilog testbench 1	SystemVerilog testbench 2	SystemVerilog testbench 3	SystemVerilog testbench 4	SystemVerilog testbench 5
Coverage	Coverage 1	Coverage 2	Coverage 3	Coverage 4	Coverage 5
Constraint solver	Constraint solver 1	Constraint solver 2	Constraint solver 3	Constraint solver 4	Constraint solver 5
Assertions	Assertions 1	Assertions 2	Assertions 3	Assertions 4	Assertions 5
Structured methodology	Structured methodology 1	Structured methodology 2	Structured methodology 3	Structured methodology 4	Structured methodology 5
Verilog	Verilog 1	Verilog 2	Verilog 3	Verilog 4	Verilog 5
SystemC	SystemC 1	SystemC 2	SystemC 3	SystemC 4	SystemC 5
VHDL	VHDL 1	VHDL 2	VHDL 3	VHDL 4	VHDL 5
Integrated Development Environment (IDE)	Integrated Development Environment (IDE) 1	Integrated Development Environment (IDE) 2	Integrated Development Environment (IDE) 3	Integrated Development Environment (IDE) 4	Integrated Development Environment (IDE) 5
Debug	Debug 1	Debug 2	Debug 3	Debug 4	Debug 5
Regression management	Regression management 1	Regression management 2	Regression management 3	Regression management 4	Regression management 5
Planning	Planning 1	Planning 2	Planning 3	Planning 4	Planning 5
Multi-voltage (low power) simulation	Multi-voltage (low power) simulation 1	Multi-voltage (low power) simulation 2	Multi-voltage (low power) simulation 3	Multi-voltage (low power) simulation 4	Multi-voltage (low power) simulation 5
Verification IP (VIP)	Verification IP (VIP) 1	Verification IP (VIP) 2	Verification IP (VIP) 3	Verification IP (VIP) 4	Verification IP (VIP) 5
FPGA-based prototyping	FPGA-based prototyping 1	FPGA-based prototyping 2	FPGA-based prototyping 3	FPGA-based prototyping 4	FPGA-based prototyping 5
Virtual prototyping	Virtual prototyping 1	Virtual prototyping 2	Virtual prototyping 3	Virtual prototyping 4	Virtual prototyping 5
Emulation	Emulation 1	Emulation 2	Emulation 3	Emulation 4	Emulation 5

11. Which of the following methods do you leverage to perform software verification/validation on your RTL? (Check all that apply.)

Which of the following methods do you leverage to perform software verification/validation on your RTL? (Check all that apply.) Virtual prototyping

FPGA-based prototyping

Emulation

Hardware-assisted Simulation (acceleration)

12. Which of the following is most likely to occur (or has occured most frequently) in your organization?

Which of the following is most likely to occur (or has occured most frequently) in your organization? Delay/delayed tape out to fix all (or most) bugs

Develop/developed workaround(s) to known RTL bug(s) to minimize/eliminate schedule delays

13. Do you conduct low power verification on your designs?

Do you conduct low power verification on your designs? Yes

14. Please rank the importance of the following low power verification capabilities/technologies. (1 is least important; 5 is most)

	1	2	3	4	5
Accuracy of low power simulation	*Please rank the importance of the following low power verification capabilities/technologies. (1 is least important; 5 is most) Accuracy of low power simulation 1	Accuracy of low power simulation 2	Accuracy of low power simulation 3	Accuracy of low power simulation 4	Accuracy of low power simulation 5
Ability to simulate standby, back-bias and DVS techniques	Ability to simulate standby, back-bias and DVS techniques 1	Ability to simulate standby, back-bias and DVS techniques 2	Ability to simulate standby, back-bias and DVS techniques 3	Ability to simulate standby, back-bias and DVS techniques 4	Ability to simulate standby, back-bias and DVS techniques 5
Native low power simulation	Native low power simulation 1	Native low power simulation 2	Native low power simulation 3	Native low power simulation 4	Native low power simulation 5
Simulation integration with debugger	Simulation integration with debugger 1	Simulation integration with debugger 2	Simulation integration with debugger 3	Simulation integration with debugger 4	Simulation integration with debugger 5
Automated low power functional coverage	Automated low power functional coverage 1	Automated low power functional coverage 2	Automated low power functional coverage 3	Automated low power functional coverage 4	Automated low power functional coverage 5
Ease of use of low power simulation	Ease of use of low power simulation 1	Ease of use of low power simulation 2	Ease of use of low power simulation 3	Ease of use of low power simulation 4	Ease of use of low power simulation 5
Capacity of designs that can be handled by low power simulation	Capacity of designs that can be handled by low power simulation 1	Capacity of designs that can be handled by low power simulation 2	Capacity of designs that can be handled by low power simulation 3	Capacity of designs that can be handled by low power simulation 4	Capacity of designs that can be handled by low power simulation 5
Comprehensiveness of static low power checks	Comprehensiveness of static low power checks 1	Comprehensiveness of static low power checks 2	Comprehensiveness of static low power checks 3	Comprehensiveness of static low power checks 4	Comprehensiveness of static low power checks 5
Integration of static low power checks with back-end tools	Integration of static low power checks with back-end tools 1	Integration of static low power checks with back-end tools 2	Integration of static low power checks with back-end tools 3	Integration of static low power checks with back-end tools 4	Integration of static low power checks with back-end tools 5
GUI for low power debug	GUI for low power debug 1	GUI for low power debug 2	GUI for low power debug 3	GUI for low power debug 4	GUI for low power debug 5
Performance and capacity of static low power checker	Performance and capacity of static low power checker 1	Performance and capacity of static low power checker 2	Performance and capacity of static low power checker 3	Performance and capacity of static low power checker 4	Performance and capacity of static low power checker 5
Ease of use of low power static checker	Ease of use of low power static checker 1	Ease of use of low power static checker 2	Ease of use of low power static checker 3	Ease of use of low power static checker 4	Ease of use of low power static checker 5
Support for CPF power format	Support for CPF power format 1	Support for CPF power format 2	Support for CPF power format 3	Support for CPF power format 4	Support for CPF power format 5
Support for advanced IEEE 1801 (UPF) power format	Support for advanced IEEE 1801 (UPF) power format 1	Support for advanced IEEE 1801 (UPF) power format 2	Support for advanced IEEE 1801 (UPF) power format 3	Support for advanced IEEE 1801 (UPF) power format 4	Support for advanced IEEE 1801 (UPF) power format 5

15. Which commercial verification IP (VIP) do you use or have a need for today?

Which commercial verification IP (VIP) do you use or have a need for today? AMBA AXI

AMBA AHB

AMBA APB

PCIe

USB 2.0

USB 3.0

SATA

Ethernet

OCP

HDMI

MIPI

PCI

Memory

I don't use or have a need for commercial VIP

Other (please specify)

16. Please rank the importance of the following VIP features. (1 is least important; 5 is most)

	1	2	3	4	5
Test planning features integrated with functional coverage	*Please rank the importance of the following VIP features. (1 is least important; 5 is most) Test planning features integrated with functional coverage 1	Test planning features integrated with functional coverage 2	Test planning features integrated with functional coverage 3	Test planning features integrated with functional coverage 4	Test planning features integrated with functional coverage 5
Integration of functional coverage with simulator reports	Integration of functional coverage with simulator reports 1	Integration of functional coverage with simulator reports 2	Integration of functional coverage with simulator reports 3	Integration of functional coverage with simulator reports 4	Integration of functional coverage with simulator reports 5
Complete functional coverage for the protocol	Complete functional coverage for the protocol 1	Complete functional coverage for the protocol 2	Complete functional coverage for the protocol 3	Complete functional coverage for the protocol 4	Complete functional coverage for the protocol 5
Access to Test Suites	Access to Test Suites 1	Access to Test Suites 2	Access to Test Suites 3	Access to Test Suites 4	Access to Test Suites 5
Ease of use: More examples and docs	Ease of use: More examples and docs 1	Ease of use: More examples and docs 2	Ease of use: More examples and docs 3	Ease of use: More examples and docs 4	Ease of use: More examples and docs 5
Ease of use: VIP configuration tools	Ease of use: VIP configuration tools 1	Ease of use: VIP configuration tools 2	Ease of use: VIP configuration tools 3	Ease of use: VIP configuration tools 4	Ease of use: VIP configuration tools 5
Error injection	Error injection 1	Error injection 2	Error injection 3	Error injection 4	Error injection 5
Protocol visualization and debug features	Protocol visualization and debug features 1	Protocol visualization and debug features 2	Protocol visualization and debug features 3	Protocol visualization and debug features 4	Protocol visualization and debug features 5
Performance	Performance 1	Performance 2	Performance 3	Performance 4	Performance 5
Better access to on-site support	Better access to on-site support 1	Better access to on-site support 2	Better access to on-site support 3	Better access to on-site support 4	Better access to on-site support 5
Protocol-based services	Protocol-based services 1	Protocol-based services 2	Protocol-based services 3	Protocol-based services 4	Protocol-based services 5
Quality	Quality 1	Quality 2	Quality 3	Quality 4	Quality 5
Number of other companies using the VIP	Number of other companies using the VIP 1	Number of other companies using the VIP 2	Number of other companies using the VIP 3	Number of other companies using the VIP 4	Number of other companies using the VIP 5
Turn-around time for questions and support	Turn-around time for questions and support 1	Turn-around time for questions and support 2	Turn-around time for questions and support 3	Turn-around time for questions and support 4	Turn-around time for questions and support 5

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Verification Complexity Surveyhttp://www.synopsys.com

Survey Questions

Verification Complexity Survey
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