Verification Complexity Survey

Survey Questions

 
Please complete our brief "Verification Complexity" survey for a chance to win a free Apple iPad.

Your answers will remain confidential.
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1. What is your job title?
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2. What category best describes your current or most recent design project?
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3. What is the size (in instances) of your current or most recent design?
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4. For what is your current or most recent design targeted?
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5. If you selected "ASIC / ASSP / Standard cells" or "Both" in question #4 above, what is the process geometry of your current or most recent design?
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6. How many interface and bus protocols are supported in your current or most recent design?
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7. For your current or most recent design, what percentage of reused lines of RTL are/were used at chip level (compared to total lines of RTL)?
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8. For your current or most recent design environment, what is/was the ratio of lines of code in testbench to lines of code in RTL?
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9. Which verification capabilities/technologies are/were used in your current or most recent project? (Check all that apply.)
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10. Please rank the importance of each of the following capabilities/technologies. (1 is least important; 5 is most important.)
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SystemVerilog testbench
Coverage
Constraint solver
Assertions
Structured methodology
Verilog
SystemC
VHDL
Integrated Development Environment (IDE)
Debug
Regression management
Planning
Multi-voltage (low power) simulation
Verification IP (VIP)
FPGA-based prototyping
Virtual prototyping
Emulation
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11. Which of the following methods do you leverage to perform software verification/validation on your RTL? (Check all that apply.)
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12. Which of the following is most likely to occur (or has occured most frequently) in your organization?
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13. Do you conduct low power verification on your designs?
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14. Please rank the importance of the following low power verification capabilities/technologies. (1 is least important; 5 is most)
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Accuracy of low power simulation
Ability to simulate standby, back-bias and DVS techniques
Native low power simulation
Simulation integration with debugger
Automated low power functional coverage
Ease of use of low power simulation
Capacity of designs that can be handled by low power simulation
Comprehensiveness of static low power checks
Integration of static low power checks with back-end tools
GUI for low power debug
Performance and capacity of static low power checker
Ease of use of low power static checker
Support for CPF power format
Support for advanced IEEE 1801 (UPF) power format
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15. Which commercial verification IP (VIP) do you use or have a need for today?
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16. Please rank the importance of the following VIP features. (1 is least important; 5 is most)
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Test planning features integrated with functional coverage
Integration of functional coverage with simulator reports
Complete functional coverage for the protocol
Access to Test Suites
Ease of use: More examples and docs
Ease of use: VIP configuration tools
Error injection
Protocol visualization and debug features
Performance
Better access to on-site support
Protocol-based services
Quality
Number of other companies using the VIP
Turn-around time for questions and support
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